Recently, with the miniaturization of semiconductor integrated circuits, variations in delay and leak current (delay variation and leak current variation) due to process have increased. Delay means the time consumed for the input and output of a signal with respect to an element or between elements in a circuit. A leak current means a current that leaks at a portion in an electrical circuit where current should not normally flow.
As a technique for taking into consideration such variations and estimating the delay and the leak current of a target circuit with such variations, statistical delay analysis (statistical static timing analysis (SSTA)) and statistical leak analysis have been proposed. SSTA is a technique for adjusting estimation of timing by providing the variation of delay of each element in the target circuit as a probability density distribution, and treating the delay of the entire circuit statistically.
On the other hand, the delay variation and the leak current variation are known to have a correlation with each other since both are caused by the process. For example, the delay and the leak current have a trade-off relationship in which the smaller the delay is, the greater the leak current becomes. Thus, the correlation between delay and leak current needs to be analyzed for accurate yield analysis of the target circuit.
Conventionally, as a technique for correlation analysis between delay and leak current, a Monte Carlo simulation has been proposed in which a delay analysis tool (static timing analysis (STA)) and a leak analysis tool are iteratively executed. In correlation analysis between delay and leak current, an approximation technique has also been proposed in which the delay distribution is modeled as a normal distribution (see, for example, Srivastava, Ashish, et al, “Accurate and Efficient Gate-Level Parametric Yield Estimation Considering Correlated Variations in Leakage Power and Performance,” Proc. DAC2005, p. 535-540).
However, in the Monte Carlo simulation, for accurate correlation analysis, the delay analysis tool and the leak analysis tool need to be iteratively executed several thousands of times, consuming more time for the correlation analysis and thus resulting in a longer time period for design.
On the other hand, according to the technique in which the delay distribution is modeled as a normal distribution, the accuracy of analysis may be reduced with respect to a circuit that includes many subcircuits operating in parallel, since the delay distribution of the entire circuit is likely to become a non-normal distribution, resulting in a re-execution of the circuit design, an increased load on the designer, and a longer design period.